Computer architectures which utilize parallel or synchronous processing hardware and software are known. Such architecture are particularly known for increasing the speed at which computationally sensitive data is processed.
Typical prior art synchronous processing architectures are specially designed to accommodate a particularly demanding processing problem. These specialized designs usually result in a system that has separate processing functions allocated to separate hardware subsystems, an approach which is both costly and inflexible. Such an organization makes it particularly difficult to reallocate processor resources between hardware subsystems as requirements change. In addition, the unique hardware of each subsystem demands its own design effort.
It is, accordingly, an object of the invention to provide a high speed data processor which is more flexible and less costly than existing processors with comparable processing power.
It is another object of the invention to provide a monolithic processor element which may be paired with other processor elements to form an efficient and programmable synchronous processing system.
Still another object of the invention is to provide methods for transferring and collecting data communicated between processor elements in a digital data processing system.
These and other objects will be apparent in the specification which follows.